The present invention relates to semiconductor devices and methods of fabricating the same, and more particularly, to nonvolatile memory devices and methods of fabricating the same.
Semiconductor memory devices may be classified into volatile memory devices and nonvolatile memory devices, depending on whether they need a power supply applied to retain data. Volatile memory devices, such as dynamic random access memories (DRAMs) and static random access memories (SRAMs) typically have a high operating speed but need a power supply applied to retain data. On the other hand, nonvolatile memory devices, such as flash memory devices, can typically retain data even when their power supply is interrupted. Therefore, the nonvolatile memory devices are generally widely used in portable electronic devices, the demand for which is rapidly on the rise.
A decrease in the price of a semiconductor device generally requires an increase in the integration degree thereof. However, such an increase in the integration density of memory devices may lead to various technical problems in a manufacturing process thereof. In particular, the increase in the integration density manufacturing process thereof. In particular, the increase in the integration density generally results in a decrease in the distance between adjacent wordlines, which may make it difficult to improve the structure and characteristics of a nonvolatile memory device. For example, a nonvolatile memory device with control and floating gate electrodes generally must have a sufficiently large coupling ratio for a rapid and effective operation, but a decrease in the distance between wordlines may make it difficult to obtain the desired coupling ratio.
More specifically, the coupling ratio may be understood as a transfer efficiency of a voltage from the control gate electrode to the floating gate electrode, which may be determined based on a distance between the control and floating gate electrodes, a dielectric constant of an insulating layer interposed therebetween, and a facing area therebetween. An increase in the coupling ratio typically requires a decrease in the distance between the electrodes and/or an increase in the dielectric constant of the insulating layer. Some attempts based on such a requirement are, however, being confronted by technical limitations accompanied by high integration density. Generally, using the presently available technology, the best method for increasing the coupling ratio may be to increase a facing area between the electrodes. However, in the prior art, the increase in the facing area generally leads to other problems, such as an increase in an electrical interference between the adjacent wordlines.
FIG. 1 is a cross sectional view illustrating a process of fabricating a cell array of a conventional flash memory. Referring to FIG. 1, device isolation layer patterns 20 defining active regions 12 are disposed in predetermined regions of a semiconductor (integrated circuit) substrate 10. A floating gate electrode 30 is disposed on the active region 12, and a gate insulating layer 25 is interposed between the floating gate electrode 30 and the active region 12. A control gate electrode 50 is disposed on the floating gate electrodes 30 that intersects the active regions 12 and the device isolation layer patterns 20. The control gate electrode 50 is used as a wordline for selecting one of memory cells of a cell array. A gate interlayer insulating layer 40 is interposed between the control gate electrode 50 and the floating gate electrode 30.
In the conventional art, the gate interlayer insulating layer 40 generally contacts the top and side surfaces of the floating gate electrode 30, as illustrated in FIG. 1, and the coupling ratio is typically proportional to the contact area therebetween. As the width l of the floating gate electrode 30 and the distance d between the floating gate electrodes 30 generally must be reduced for high integration, an increase in the facing area (i.e., an increase in the coupling ratio) is generally possible only by an increase in the height h of the floating gate electrode 30. The increase in the height of the floating gate electrode 30 involves an increase in a facing area with an adjacent wordline, which may cause the electrical interference as described above. The increase in electrical interference may cause data stored in a given cell to vary.
Various methods for modifying the sectional shape of the floating gate electrode have been proposed to reduce the above electrical interference. One of the methods is to form the floating gate electrode so that it has a “U” shaped section. This method, however, may cause some technical problems in a peripheral circuit region in which wide active regions are formed.
More specifically, in the case of a cell array region with narrow active regions, the sidewalls of device isolation layer patterns surrounding the active region are generally formed perpendicular to a semiconductor substrate. On the contrary, in the case of a peripheral circuit region with a wide active region, the sidewalls of a device isolation layer pattern may have a negative slope (i.e., θ<90°) as illustrated in FIG. 2. This negative slope may cause the device isolation layer pattern to act as an undesirable etch mask in the patterning process used in forming the floating gate electrode.
In particular, according to the conventional method in which the floating gate electrode is formed to have a “U” shaped section as illustrated in FIG. 2, a floating gate conductive layer 30′ is generally formed to conformally cover the exposed surface of a device isolation layer pattern 20 and the top surface of a gate insulating layer 25, and a gate interlayer insulating layer 40 is conformally formed on the floating gate conductive layer 30′. However, as the device isolation layer pattern 20 with a negative slope may act as an etch mask, a residue of the gate interlayer insulating layer 40 may be formed (remain) around the sidewalls of the device isolation layer pattern 20 during a subsequent process of removing the gate interlayer insulating layer 40 from a peripheral circuit region. This residue of the gate interlayer insulating layer 40 may act as an etch mask causing a residue of the floating gate conductive layer 30′ during the subsequent patterning process. This residue of the floating gate conductive layer 30′ may cause an electrical defect, such as a bridge. In the prior art, to address such a problem, an over-etching process may be performed to more completely remove the gate interlayer insulating layer 40 from the peripheral circuit region.
However, as the above over-etching process typically recesses the top surface of the device isolation layer pattern 20, a gate electrode formed in a subsequent process approaches the top surface of the semiconductor substrate 10. This may lead to the formation of parasitic transistors that may cause a hump phenomenon. When considering the fact that transistors with good electrical characteristics, such as sensing circuits, are typically disposed in the peripheral circuit region, the problem due to the parasitic transistors may be fatal to the yield of flash memory devices.